The present invention relates to a processing apparatus such as a high-performance microprocessor.
Various types of very large scale integration (VLSI) microprocessors have been proposed along with the recent development of microcomputers. However, a VLSI microprocessor for software engineers, i.e., a VLSI microprocessor compatible with system development software has not yet been proposed.
A central processing unit (CPU) preferably transfers and processes (logic and arithmetic operations) data and deals with decision blocks of a flow to satisfy the needs of a user. With a conventional microprocessor, the internal structure is not hierarchical. In addition, a low order level machine language is mainly used such that a programmer must access registers in the VLSI microprocessor, which is far from what the programmer really wants to perform. Although some conventional microprocessors have high order level instructions, these instructions cannot be constructed systematically with low order level instructions. Thus, almost of conventional microprocessors have instructions with a so-called semantic gap.
In the computer industry, there are strong demands for improvement of software productivity and reliability (high quality). These demands can be rapidly satisfied by high-class procedures such as system specification definitions, system analysis, system design and software design. However, the programming required to achieve high performance and higher functions of the VLSI microprocessors is complicated since machine instructions are low order level. As a result, many bugs tend to occur. In order to solve problems of such programming, hierarchical programming techniques and corresponding system description languages are proposed. Typical examples are Pascal, C, PL/M and the like. A strong Ada language is being put into practice. However, since compilers of these languages translate the languages into machine languages of given microprocessors, memory usage efficiency is slightly degraded and the processing rate is slightly decreased. Under these circumstances, in industrial systems (FA or factory automation, including industrial robots) which comprise microprocessors, there are few programmers who wish to create control programs by system description languages. Although most of the basic software packages require a maximum use of highly reliable tools such as operating systems and compilers, these packages are written by assembler languages greatly influenced by the internal structure of the microprocessors. Therefore, a demand has arisen for development of a microprocessor wherein intermediate codes of the system description language are directly processed as the machine language.
FIG. 1 is a block diagram showing a general configuration of a conventional microprocessor. This microprocessor comprises an external address bus 3, an external data bus 5, an external control bus 7, an internal data bus 9, a machine instruction bus 11, bus control logic circuits 13, an address register file 15, an instruction register 17, an instruction decoder 19, a micro operation sequence control logic circuit 21, a data register file 23 and an ALU 25. With the above configuration, the register 17 fetches an instruction from the bus 5 through the bus 11. The instruction fetched by the register 17 is decoded by the decoder 19, and the decoded result is supplied to the circuit 21. The circuit 21 comprises a programmable logic array (PLA) for generating micro operation instructions. The circuits 13, the file 15, the register 17, the decoder 19, the file 23, and the ALU 25 are controlled by the micro operation instructions sequentially generated by the circuit 21. The ALU 25 receives data through the bus 9 under the control of the circuit 21 and processes the received data. The resultant data is sent onto the bus 9.
In the conventional microprocessor, a machine instruction fetched by the register 17 comprises an operation code field 27 and an operand field 29, as shown in FIG. 2. The operation code in the field 27 is flatly assigned to an operation code table. The operand field 29 stores physical objects such as addresses of areas for storing data such as immediate data or data as objects for the registers and operation objects. A bit pattern of the machine instruction expressed by these fields is read out from the register 17 and is decoded by the decoder 19.
However, in the conventional microprocessor wherein the bit pattern of the machine instruction is read out from the register 17 and is decoded and executed, the following drawbacks are presented when high performance is required:
(i) Since a machine instruction is simply subjected to semantic assignment and not classified into functional blocks, the circuit 21 and the decoder 19 for decoding the instruction read out from the register 17 must have a complicated arrangement when a high order level instruction is to be executed. As a result, time and cost for design, check and evaluation are increased.
(ii) The operand field is an object data type and is not abstracted, and physical registers, memories and port address generation machanism in the microprocessor are designated by a user. For this reason, the operand field has a weak association with an operation type of the machine instruction, and the object data type is present independently of the operation type. As a result, a physical register number and an internal data bus width must be selected and a general-purpose circuit block must be modified for a designated usage so as to perform a specific operation such as addition of integers. The micro operation sequence becomes complicated, and the number of signal lines to be controlled by the micro operation instruction is increased. In addition, since microprogramming must be performed, the circuit 21 for storing a micro operation sequence in correspondence with the machine instruction must have a large size and the signal lines are excessively concentrated on the circuit 21. This means that a number of signal lines run parallel in a single chip. Furthermore, since the size of the circuit 21 is greatly increased, the layout of elements in the chip is greatly limited. As a result, interwiring between the circuit blocks becomes difficult.
(iii) In order to improve a model or develop microprocessors of the same family or a high-performance microprocessor, various circuit blocks, a micro operation sequence, various types of control logic which are indispensable for such development and the wiring for connecting these circuits must be designed and arranged each time since a hierarchical structure is not provided. As a result, an available function library is not prepared.
(iv) High reliability is often required to create a high-performance system such as a real-time multiple parallel processing system. In this case, it is dangerous to allow an assembler program which is not easily understood and is sophisticated. Under this condition, it is also difficult to make a further improvement and proper maintenance. In order to overcome these drawbacks, system description languages such as Pascal, C and Ada have been recently proposed. Since the microprocessor has the above drawbacks, a highly efficient machine instruction sequence cannot be easily created by a compiler programmer. Conventional microprocessors are not inherently compatible with these system description languages and large system configuration.
When the conventional microprocessor having the configuration shown in FIG. 1 is formed on a single chip, the files 15 and 23, the ALU 25, the register 17 and the like are formed on the chip first. The various machine instruction functions are forcibly performed by the decoder 19 and the circuit 21. In this case, the hierarchical functional blocks are not provided. The decoder 19 and the logic circuit 21 are sophisticated to decrease the chip size. It is expensive and time-consuming to design and test the system and expand and modify its functions.
In particular, the program cannot be easily understood except by the copy writer himself, and the technical contribution to organizations and society is small. Even if the program is based on known techniques, it can be regarded as a unique invention, thereby precluding technical development and popularity.
Control signal exchange between the circuit 21 and other components becomes excessively congested when high-performance is to be achieved. The length and space of wiring in the chip are increased. In addition, when high performance is achieved, a PLA constituting the circuit 21 must have a large size, and interwiring between the respective components is difficult. In addition, each random logic for directly controlling the corresponding component must be modified when a microprocessor with new functions is designed and manufactured, resulting in large losses in time and cost.
FIG. 3 is a block diagram showing the general configuration of a conventional microprocessor. A microprocessor 31 comprises an external bus 33, a bus control section 35, a bus switching controlling section 37, a machine instruction bus 39, an instruction register 41, an instruction decoder 43, a micro operation sequence control logic circuit 45, random control logic circuits 47, internal data buses 49 and 51, address registers 53, data registers 55, temporary registers 57, an ALU 59 and flags 61.
In the microprocessor 31, an instruction is fetched from the bus 33 to the register 41 through the sections 35 and 37 and the bus 39. The instruction stored in the register 41 is decoded by the decoder 43, and a decoded result is supplied to the circuit 45. The circuit 45 comprises a programmable logic array (PLA) for generating a micro operation instruction. The circuits 47 are controlled in response to the micro operation instruction. The circuits 47 constitute parts of the section 35, the decoder 43, the registers 53, 55 and 57 and the ALU 59 which are controlled when the circuits 47 are controlled.
The circuit 45 stores a number of sequences which are of different type and function level so as to cause the sequences to interfere with each other (i.e., parts of the sequences are commonly used). Upon operation of the micro instruction as an output from the circuit 45, a discrete physical data structure is accessed through the circuits 47, and control operation continues in a strong association with the random control logic circuits in the section 35.
In the microprocessor described above, since the system design of hierarchical functional blocks is not established in accordance with the operation specifications, the circuit blocks are weakly independent of each other. Physical low order level blocking such as blocking for registers, buses, switching circuits, selectors, encoders and decoders is performed. These blocks are entirely controlled by the circuit 45.
The operating time of each circuit block, and a relationship with another circuit block for exchanging resources such as data, a control signal, a status signal, and a clock signal which are generated during the operation cannot be solely determined. For this reason, it is difficult to effectively achieve increases in operating speed and yield in the system design level.
When a high-performance VLSI microprocessor is developed, changes in micro operation sequence and data structure strongly interfere with another block. It is difficult to design and test products, resulting in a long development period and high cost.
For example, FIGS. 4 and 5 show examples of a controlled status of the conventional microprocessor. Referring to FIG. 4, when a system as a target to be controlled is defined as C, a plurality of controlling systems A and B are provided to control the system C. In addition to this drawback, the systems A and B greatly interfere with each other. However, referring to FIG. 5, a controlled system C is directly operated by a single controlling system D. The system D is driven by a plurality of controlling systems A and B. In the same manner as in the case of FIG. 4, the system C is operated in accordance with the status of the systems A and B. It should be noted that each controlling system comprises a logic section 63 and a status storage section 65. The situation is more crucial since the status storage of the system C is not locally but directly updated by the systems A, B and D. For this reason, a slight modification is made for not only the timing of the system C but also the function thereof. As a result, the operation of the system C cannot be stably estimated.
As is apparent from the above description, it is very difficult to design a system wherein the operating speed and the yield of products are effectively increased in the system design level and to test the finished products. In addition, the development period is prolonged and the manufacturing cost is high.
Furthermore, the conventional microprocessor ICs are classified into an all dynamic microprocessor in which the internal system comprises dynamic memory circuits 67 and control/judgement circuits 69, as shown in FIG. 6, and an all static microprocessor in which the internal structure comprises static memory circuits 71 and control/judgement circuit blocks 73, as shown in FIG. 7. As shown in FIG. 8, each circuit 67 has an input read-in gate 75 and an output enable gate 77. Each of the gates 75 and 77 comprises a clocked inverter circuit 79 shown in FIG. 10. Each static memory circuit 71 comprises an input read-in gate 75, an output enable gate 77, a clocked inverter 80 and an inverter 81, as shown in FIG. 9.
Among the conventional microprocessors having the arrangements described above, the all dynamic microprocessor has a smaller number of elements than that of the all static microprocessor. More specifically, six elements are omitted from each circuit of the all dynamic microprocessor as compared with the number of elements of each circuit of the all static microprocessor. The chip size of the all dynamic microprocessor is smaller than that of the all static microprocessor, thereby decreasing the manufacturing cost. However, the all dynamic microprocessor has a narrow operating frequency range. In addition, when the clock is disabled, an operational error often occurs.
The all static microprocessor has a wide operating frequency range and is properly operated even if the clock is disabled, thereby decreasing power consumption. However, the number of elements of the all static microprocessor is larger than that of the all dynamic microprocessor. Therefore, the chip size of the all static microprocessor is larger than that of the all dynamic microprocessor, resulting in high cost.
When the dynamic and static microprocessors are used together, the operation timings of the system as a whole are very complicated, resulting in inconvenience.